III-V compounds offer a number of advantages over silicon with respect to the operation of semiconductor devices such as field-effect transistors. The heterointegration of III-V compounds on materials such as silicon allows the co-integration of III-V nFETs with SiGe pFETs. III-V and CMOS is one possible option for sub-10 nm technology nodes.
III-V semiconductors have larger lattice constants than silicon, so integrating them on silicon is challenging. Methods for integrating III-V semiconductors on silicon have included blanket III-V growth and aspect ratio trapping (ART). Blanket growth traps most of the misfit dislocations near the lattice mismatched interface, but threading dislocations still reach the surface semiconductor material. Defect densities are in the 1e7 to 1e9/cm2 range. The deposition of thick III-V layers is required when using the blanket deposition technique.
Aspect ratio trapping is an effective technique to trap threading dislocations, thereby reducing the dislocation density of lattice mismatched materials grown on silicon. The ART technique can be performed using thinner III-V layers. Trenches are employed for trapping misfit threading dislocations by stopping their propagation. The III-V material is grown in narrow trenches. The dislocations end at the trench walls, but fairly high defect densities up to 1e8/cm2 can still be observed.
The performance of devices fabricated using dissimilar semiconductor materials can be materially affected by defects that cause abrupt changes in electrical and/or optical properties. Adverse effects due to misfit defects and threading dislocations should be minimized or avoided in the fabrication of electronic devices incorporating such semiconductor materials.